In general, a system bus, e.g. north bridge, south bridge, peripheral component interconnect (PCI) bus, etc., may be used for transferring packets and transactions. Packets may be posted write packets or non-posted write packets. Posted write packets receive acknowledgement signals but non-posted packets do not receive acknowledgement signals.
A system bus in a host or a peripheral bus, e.g., hyper transport, PCI express, PCI extended, front side bus, advance microcontroller bus architecture, etc., requires certain ordering for different packets. For example, in one conventional system a non-posted packet cannot be transmitted ahead of a posted packet if the posted packet originated before the non-posted packet.
Referring now to FIG. 1, a conventional system 100 is shown for ensuring that posted packets that originated before non-posted packets are transmitted ahead of the non-posted packets. The conventional system 100 comprises an input bus, a first random access memory (RAM) 110 and a second RAM 120. The first RAM 110 stores non-posted packets. For example, N1 packet may be stored in location 0 and N2 packet may be stored in location 1.
The address at which the last non-posted packet is stored is used to tag posted packets arriving after the last non-posted packet. The tag corresponds to the address location at which the last non-posted packet is stored. For example, the address 0 for the non-posted packet N1 is used to tag posted packets P1 and P2 arriving after the non-posted packet N1. The posted packets P1 and P2 are each stored in their corresponding locations, e.g., address 0 and 1 respectively, in the second RAM 120 along with their tags, e.g., tag=0.
A non-posted packet, e.g., N2, may be received after the posted packet P2. Accordingly, the non-posted packet N2 is stored in the first RAM 110 in location 1. The address at which the non-posted packet N2 is stored is used to tag posted packets arriving after the non-posted packet N2, e.g., posted packet P3. As such, when posted packet P3 is received, it may be stored in the second RAM 120, e.g., address 2, along with its corresponding tag, e.g., tag=1. The tags stored along with posted packets are used to ensure that posted packets that originated before the non-posted packets are transmitted ahead of the non-posted packets originating after.
According to one enforcement rule, a non-posted packet can be transmitted ahead of a posted packet as long as the tag associated with the posted packet indicates that the posted packet was received after the non-posted packet. According to another rule, a non-posted packet can be transmitted if the RAM 120 storing posted packets is empty. For example, the ordering of packets received may be N1, P1, P2, N2 and P3 whereas the ordering of packets read may be N1, P1, P2, P3, N2 or P1, P2, P3, N1, N2 or P1, N1, P2, P3, N2 or P1, N1, P2, N2, P3, for instance.
Unfortunately, tagging posted packets with the address at which the last non-posted packet is stored increases the amount of storage required to implement the scheme. For example, tagging posted packets with the address at which the last non-posted packet is stored requires more flip-flops to store the tags and the addresses in comparison to storing the packets alone. As a result, the amount of storage, complexity and cost increase.
Unfortunately, using the same RAM for both non-posted packets and posted packets is not possible for conventional tagging. As a result, the number of required RAMs increases which increases manufacturing cost and complexity. Moreover, conventional tagging is difficult for packets received from different system buses because ordering enforcement is not feasible between different system buses. Additionally, conventional tagging becomes very difficult if the address at which the last non-posted packets are stored cannot be determined, e.g., when a single RAM is shared by different units.